Priority interrupt monitoring system



Nov. 30, 1965 Filed Aug. 10, 1961 SCANNER -01 eusv'bnz READYSIQIINTERRUPT R. BENGHIAT PRIORITY INTERRUFT MONITORING SYSTEM 16 Sheets-Sheet 1 TRANSDUCER SCANNER IN PUTS (MULTIPLEXER) ADC FA. REG.

s z xQ MANUAL SWITC HES OTHER INPUTS CONTROL AND REG. MEANS STORAGEARITHMETIC AND PROGRAMMER MEANS (COMPUTER) OUTPUT DISPLAY DEVICE TIMERPULSES ODD PATCHBOJIRD PRIORITY LEVEL OUTPUT DE VICE PS EUDO DEMAND 5SIGNAL LINE DEMAND SIGNAL SAMPLING GATES TERMINALS C SIT DEMAND SIGNALTE RMINAB PATH-I 80420 1 SAMPLING GATES C BIT PRIORITY LEVEL SELECTIONTERMINALS SETI;

STATUS IEESET or 509/ "SIGNAL GATES C BIT GROUPING GATES AND REGISTERSSET R INTERRU PT REGISTER OUTPUT DEVICE INDI R BIT CATO R uzcoouva cares(ms m. ADDR FROM C BITS TO O ERATIONS REGISTER PSEUDO DEMAND smnm. FROMOPER.

REG.(FROM s23) PRIORITY SCANNER TO COMPUTER CONTROL UNIT RESET SIGNALFROM om: REG. (men 523) SIGNALS) J30 GATES AND ADDRESS COUNTER TOCOMPUTER ADDRESS REGISTER (FROM 5|?) (FROM srslo) I N VEN TOR.

RALPH BENGHIAT Nov. 30, 1965 R. BENGHIAT 3,

PRIORITY INTERRUPT MONITORING SYSTEM Filed Aug. 10, 1961 16 Sheets-Sheet3 I 1 I l i Nov. 30, 965 R. BENGHIAT 3,221,309

PRIORITY INTERRUPT MONITORING SYSTEM Filed Aug. 10, 1961 16 Sheets-Sheet7 3% I 41-4 1 40 I F F 15 91, 4l-5 5043-? F 75 4.144 4P3 n-|2 5A Fn 724P6 s1 Sm F 72 1024.1

7 1 SET; MONO STABLE 4 4 s21; I 5551 RF. TwLi M 45-2 3' 8m I 4MULTIPLEXER i I 8 3 5%6 ADDRESS I n-r29 REGISTER t L J a/: (MEANS a ourur bo (MEANS b ourpur OF A [1 CORE) 0: AN 1 CORE) OUTPUT (x PHASE PULSEmmslrs SET) TO =PHA$E 6 CORE TRIGGER PULSES USEC APART) RALPH BENGHIATT0/3 PHASE 4 TRIGGER PULSES e USEC APAELAND SPACED CYtLE k/Z @442:

02 3 uszc FROM L TRIGGER PULSES) TVS.

INVEN TOR.

Nov. 30, 1965 R. BENGHIAT 3,221,309

PRIORITY INTERRUPT MONITORING SYSTEM Filed Aug. 10, 1961 16 Sheets-Sheet8 B LEVEL l CLOCK ROUTINE CLOCK PULSE (EVERY as SECONDS) INTERRUPT STORE5E0, COUNTER INLUC. I00 oc s 'b (PR'ORITY ORDERS FOR TRANSFER TO LOC.lO/a, LEVEL 73 I00 40 (0|) LOC. IOZ O.-|030.

( (cu/v15? 1-20 2 YES (EvERY SMINUTES) 1 NO we. I03b Loc. logo,

lcopv RI MASK mans m0 ACCJ [A00 I TO COUNTER z Lac/o4 b-IO'7b N0 LOC.IO4a-IO5b 1 C COUNTER 2 =12 RESET RI YES RESTORE ONTENTS LOCJIOa-Hlb"(EVERY HOUR) To LOWER LEVEL (OPY A4 MASK DIGITS 0W0 Arr.

SIGNAL PSEUDO INTERRUPT 4 CLEAR COUNTER 2 F TRANSFER TO Loc, l08a.

LOC. l08culO9b c1. Ema COUNTER I SWITCH MULT/PL 5x52 T0 Pal/VT! l 0 1 l5 TRANSFER T0 [.06. /04a.

| I e I FlGURE 3 I FDGURE 3A I J i neuae 3B mum; 3c

| INVENTOR.

1 FIGURE: RALPH BENGHIAT TYS.

Nov. 30, 1965 R. BENGHIAT 3,221,309

PRIORITY INTERRUPT MONITORING SYSTEM Filed Aug. 10, 1961 16 Sheets-Sheet9 lbw PRODUCT Ln m r. INVENTOR 9 II a: RALPH BENGHIAT m BY A rrvs.

Nov. 30, 1965 R. BENGHIAT PRIORITY INTERRUPT MONITORING SYSTEM FiledAug. 10, 1961 MULTIPL E XER NOT BUSY INTERRUPT STORE SEQ. COUNTER INL0(. 200

TRANSFER TO LOC. ZOIQ.

LOC. 204a-205a.

( POINT COUNTER =N we. 205b- 2060.

[SWITCH MULTIPLEXER T0 NEXT Pamrl L C. 206b-208Q.

COPY R2 MASK DIGITS W10 ACC.

RESET R2 RESTORE OLD 44(C. CONTENT-S EXIT T0 LOWER LEVEL l6 Sheets-Sheetl3 4 LEVEL 2 -MULT|PLEXER INPUT ROUTINE Loc. 6Q,b(PRl0RITY ORDERS FORLEVEL 2-73 200: 40 20! (5702:; INPUT vALuE) YES LOC. 209 0,1: l

CLEAR POINT COUNTER TRANSFER TO EXIT SEQUENCE (Exrr SEQUENCE) msrrwcrroumsmuc'nou WORD 1 WORD *2 FUNCTION ADDRESS B-LINE FUNCTION ADDRESS NUMBERNUMBER an NUMBER NUMBER #M ,M r- 0 0 O 0 0 O I O 0 0 O 0 O INVENTOR,RALPH BENGHIAT A'rrvs,

Nov. 30, 1965 R. BENGHIAT 3,221,309

PRIORITY INTERRUPT MONITORING SYSTEM Filed Aug. 10, 1961 16 Sheets-Sheet14 F- 5 LEVEL 3 .fi; BINARY To DECIMAL CONVERSION ROUTINE (4 DIGITPosITIvE INTEGER) PSEUDO INTERRUPT FROM LEVEL 4 0R LEVEL 5 INTERRUPT(VALUE TO BE CONVERTED Is m Acc) m; 5m, COUNTER IN LOQ 30o LOC. 70.,b(PRIORITY ORDER FOR TRANSFER TO LOC. 30m L LS-73 300 40 31M) LOC. 30m.

LOC. 303b-305 {CLEAR WORKSPACE LOC. 3201 ADD Iooo T0 Acc.

EXCHANGE ACC. a Loc. 32o

sI-IIFT ACC. 5 ans LEFT EXCHANGE ACC. Mac. 320

LOC. 30,

[suamncr I000 mom ACC.

LOC. 302 a.

YE Is Acc. NEGATIVE g S LOC. 305a LOC.302b-303a SUBTRACT Ioo FROM ACC. J

[A00 I TO LOC. 320 j LOC. 3060. 1

15 Acc. NEGATIVE LOC.306b-307Q P LOC.307b-309o. ADD ITo Lon 32o ADD I00T0 AC.

EXCHANGE ACCiLOC. 32o

sI-IIFT ACC. 5 511's LEFT EXCHANGE Acc. LOC. 320

YES

LOC. 3Hb3l3a ADD IO TO ACC.

EXCHANGE Acc. Loc.3zo

SHIFT Am. 5 BITS LEFT ADD LOC. 320 T0 Acc.

Loc. 3l3b-3I5b y EXCHANGE A66. 8 R3 MASK DIG/TS RESET R3 I.0c.3 t -3 N0EXCHANGE are. (we. 3/9

[ Am; I TO LOC. 320 J sxrr ra LOWER LEVEL (RESULT OF CONVERSION 'N Acc')INVENTOR.

RALPH BENGHIAT I A'r-rvs,

LOC, 3o9b SUBTRACT 10 FROM ACC.

LOC. 3'0 I (Is Acc. NEGATIVE 3 YES PRIORITY INTERRUPT MONITORING SYSTEMFiled Aug. 10, 1961 16 Sheets-Sheet l5 LEVEL 4 -LOG DATA PREPARATIONROUTINE PSEUDO INTERRUPT FROM LEVELI OR LEVEL 5 INTE RRU PT STORE SEQ.coumen IN LOC.400 LOC.8Q,b(PRIORITY ORDERS FOR TRANSFER To me. 40m LEVELLOC. 40m 1 STORE Acc. m 1.06.416

CLEAR coumsre 11v LOC.4I7

I; LDC. 4020: 404 b 7 COPY A3 MASK DIGIT5 INTO AC6.

SIGNAL P.5EUDO INTERRUPT ADD I TO COUNTER LOC. 408 -4Hb l Co y DATAVALUE mrro Acc. COPY A7 MASK DIGITS no 4C6. WAIT FOR M/TEREUPT SIGNALpsauoo INTERRUPT copy R4 MASK DIGITJ INTO Act. INTERRUPT 94 ROUTINE OFLEVEL 3 LOC. 405a,:

| sroses corwaerso VALUEj LOC. 40641-4070.

YES Q COUNTER N H LOC. 40%

| TRANSFER T0 1.0:. 402a.

RESTORE OLD ACC. CONTENTS EXIT T0 LOWER LEVEL INVENTOR. RALPH BENGHMTATTYS.

United States Patent 3,221,309 PRIORITY INTERRUPT MONITORING SYSTEMRalph Benghiat, Pacific Palisades, Calif., assignor to The ScamInstrument Corporation, a corporation of Illinois Filed Aug. 10, 1961,Ser. No. 130,615 14 Claims. (Cl. 340-1725) This invention, in general,relates to industrial process monitoring systems or other systemswherein the system must examine and respond to input data as it arrives,instead of merely storing the data for future examination and use. Inthis, they diifer fundamentally from most business and scientific dataprocessing machines. For safety and efficiency, the industrial processmonitoring system must be available at all times to attend to the needsof the process. However, some aspects of the invention have a moregeneral application.

A typical present day industrial process monitoring system has anelectronic computer system including arithmetic and memory sections. Thememory section usually stores various data constants, such as high andlow alarm or control limits, scale factors, and a multiplicity ofprogram routines for carrying out different types of system operationdemanded by the process being monitored, or by various external signalsources such as manual switches and the like. The arithmetic sectioncarries out various arithmetic operations called for by the program,such as comparing the values of the process variables with the alarm orcontrol limit values by a subtractive process which indicates whether analarm or control function is to be carried out. One of the programroutines may be a normal basic routine which includes the scanning ofthe various process variables and examining the variable values foralarm conditions. The basic routine may be momentarily interrupted ormodified by the presence of various external signals calling momentarilyfor other program routines. The operation of one manual switch, forexample, may call for a program routine which changes the data constantsand the operation of another switch may call for a program routine whichreads out the stored data values to a typewriter.

Where the monitoring system almost simultaneously receives a number ofmanual demands for different program routines, the question arises as tothe order in which these demand signals are obeyed and the manner inwhich the currently active program routine is affected. If it is desiredthat all program routines be carried out in an order depending upon therelative importance or priority of the routines, the different routinesmay be assigned priority level numbers in accordance with their relativeimportance and the priority level number of a routine in progresscompared with the priority numbers of the program routines whoseoperation have been demanded. The current program is immediatelyinterrupted and replaced by the demanded program routine of a higherpriority. The point of interruption of the interrupted program routineis recorded in memory so that it can be later resumed. After completionof all demanded program routines of higher priority, the interruptedprogram is resumed.

The present invention is a substantial improvement over the basicpriority interrupt scheme just outlined by increasing the flexibilityand scope of priority assignment, simplifying the program of themonitoring system, and greatly increasing the efliciency of utilizationof input and output devices normally repeatedly used by the system.

In accordance with one aspect of the invention, certain programoperations which are normally part of a larger program routine assignedto a single priority level are given independent priority status, eventhough they are not directly demanded by external demand signals. For

3,221,309 Patented Nov. 30, 1965 example, a program sub-routine which isused in common with other program sub-routines is given an independentpriority status along with the program sub-routines which use the commonsub-routine. The common or shared routine is initiated by a programgenerated signal, referred to as a *pseudo" interrupt demand signal,which is treated by the monitoring system in the same manner as theaforementioned external or manual interrupt demand signals. It isimportant that the shared routine initially operated by a pseudointerrupt demand signal from one of the other routines benon-interruptable by the other routine or routines which share it.Otherwise, data developed by the common shared routine may be lost wheninterrupted by the latter routine. This problem is overcome by assigningthe shared routine a priority level which is higher than the programroutines which could demand its operation.

The provision of pseudo interrupt demand signals and the special programroutines operated by them results in an overall program of the highestpossible efficiency and flexibility. The pseudo interrupt demand signalgenerated in a program routine can be used not only to initiate animmediate interrupt to a program routine of higher priority as indicatedin the above shared routine example, but it can also be used to initiatethe later operation of program routines having a lower priority than thecurrently operated routine.

In accordance with another aspect of the invention, individual programroutines are set up to be initiated by not busy or ready signals fromvarious input or output devices used in the monitoring system so thatthe most efiicient use of these devices may be had. For example, thescanner or multiplexer which scans the process variables are commonlyprovided with ready signal generating means for indicating to thecomputer when it is ready to transfer data to the computer or otherinput equipment such as an analog to digital converter. The ready signalis used as a priority interrupt demand signal in the same way as theother discussed priority interrupt demand signals so that the scanningroutine is carried out immediately whenever the other demanded routinesare of lower priority. Since one of the most important functions of amonitoring system is to detect alarm values of variables or variableswhich require special control functions, the prompt operation of thescanner becomes of extreme importance.

In accordance with still another aspect of the invention, the currentactivity of the program routines is visibly indicated by theenergization of lamps or other visual indicating means assigned to therespective program routines. Since many of the routines are carried outin such a short time period that a lamp energized for such a periodwould not be visible, means are provided for extending the period ofresponse of each alarm lamp somewhat beyond the time of occurrence ofthe program routine involved. The provision of these indicating lampsgreatly facilitates the operator in his knowledge about the operation ofthe system. For example, program interrupt operations will be indicatedby seemingly steady or prolonged light indications since the activationof the program routines is extended by interrupt operations. Theactivity of uninterrupted program routines are usually indicatcd byblinking lamps, that is lights which are energized only momentarily.This aspect of the invention has application to computer systemsgenerally.

Where a large number of external program interrupt demand signals areinvolved, it may become impractical to assign each routine operated by ademand signal a different priority level. The presence of a very largenumber of demand signals and associated independent routines ofsecondary importance can encumber the speed of the monitoring system andunduly complicate the same. In accordance with another aspect of theinvention, various program routines of secondary priority status andwhich could have independent priority status are grouped together in asingle routine as sub-routines joined together by conditional transferprogram steps which branch the program to a sub-routine or sub-routinescalled for by the external demand signals involved. The presence of thelatter demand signals are stored and a single interrupt demand signal isgenerated which effects an interrupt operation to the common routinewhen it is the highest priority routine demanded by the system.

In addition to the various broad aspects of the invention just outlined,the invention has many specific aspects dealing with specific ways ofcarrying out these broad features. As will appear, some of thesespecific aspects have applications beyond the particular applicationsillustrated above. For example, one such aspect deals with a unique wayfor handling and storing information of the various external andinternal interrupt demand signals, and for examining the storedinformation. The means for storing this information is referred to as aninterrupt register. The interrupt register has provision for storingmarkers indicating momentary or persisting demand signals and successivedemand signals. A routine demanded by a persisting demand signal islocked out after it completes one cycle of operation. Also, a routinewhich is activated but not completed by a momentary signal can be causedto operate a second time automatically at a later time by the presenceof a second demand signal.

The above and other objects, advantages and features of the inventionwill become apparent upon making reference to the specification tofollow, the claims and the drawings wherein:

FIG. 1 is a basic box diagram of a monitoring system incorporating theprogram interrupt system of the present invention;

FIGS. 2 and 2A together represent a more detailed box diagram of thesystem shown in FIG. 1;

FIGS. 3, 3A, 3B, 3C and 3D represent an exemplary circuit diagram of theprogram interrupt control and register means forming part of the systemshown in FIGS. 2 and 2A;

FIG. 4 is a diagram illustrating the manner in which FIGS. 3, 3A, 3B, 3Cand 3D can be arranged to form an integral circuit diagram;

FIGS. 5, 5A and 5B show core circuit diagrams of parts of an exemplaryElliott 803 computer to which the circuit of FIGS. 3, 3A, 3B, 3C and 3Dmake connection;

FIG. 6 identifies the various types of inputs to the core circuits ofFIGS. 5, 5A and 5B;

FIG. 7 illustrates a timing diagram which relates to certain operationsperformed in the computer to certain operations performed in the programinterrupt apparatus of the present invention;

FIG. 8 illustrates the types of information which circulates in thecomputer operations register;

FIG. 9 illustrates the arrangement of the bits of information stored inthe interrupt register of the present invention;

FIG. 10 consisting of FIGS. 10(a), 10(b) and 10(0) shows the binary codeformat for the C mask bits stored in the computer memory and used toexamine and reset the contents of the interrupt register;

FIG. 11 consisting of FIGS. 11(a), 11(1)), 11(0) and 11(d) indicates theR mask bit and pseudo mask bit code group stored in the computer memoryfor resetting certain R bits in the interrupt register and forinitiating pseudo demand signals for certain priority levels;

FIG. 12 shows the format of a typed instruction word group stored in thecomputer memory;

FIG. 13 is a fiow diagram illustrating the clock routine which has beenassigned priority level No. 1;

FIG. 14 is a How diagram illustrating the multiplexer input routinewhich has been assigned priority level No. 2;

FIG. 15 is a flow diagram illustrating the binary to decimal conversionroutine which has been assigned priority level No. 3;

FIG. 16 is a flow diagram illustrating the log data preparation routinewhich has been assigned priority level No. 4; and

FIG. 17 is a How diagram illustrating the operators request routinewhich has been assigned priority level No.5.

PART IGENERAL DESCRIPTION Refer now to FIG. 1 which illustrates the useof the present invention in connection with a system for monitoringprocess or other variables in a chemical or industrial process. Thevalues of the various variables of the process may be detected bysuitable transducer devices 2, such as thermocouples in the case oftemperature variables. The individual electrical outputs of thetransducers 2 are fed to the input of a scanner or multiplexer 4. Thescanner 4 can take any one of a number of forms well known in the art,but is preferably an electronic diode matrix scanner well known in theart which can randomly select any transducer input in accordance withcontrol signals fed to an input 5 thereof. The output of the scanner 4is shown connected to the input of an analog to digital converter 6which converts an anaiog input to a binary digital output in a wellknown manner. The output of the analog to digital converter 6 is fed toa register 7 in turn connected to the input of a storage, arithmetic andprogram means generally indicated by reference numeral 8. The storage,arithmetic and programing functions carried out by this portion of thissystem is commonly carried out by electronic computers. The exact formof the computer forms no part of the present invention although, toillustrate the use of the present invention, reference will be made tothe model 803 computer manufactured by Elliott Brothers, Ltd. of London,England. A disclosure of the circuitry and mode of operation of thiscomputer will not be disclosed or explained in any great detail in thisapplication. However, such information is incorporated in a book in theScientific Library of the Patent Ofiice entitled Handbook for theNational-Elliott 803 Computer. Also, a block diagram of part of thecomputer 8 is shown in FIG. 8 and the core circuitry of those portionsof the computer to which the interrupt apparatus of the invention isconnected is shown in FIGS. 5, 5A and 53.

Where an industrial process is being monitored, it is normally necessaryfor the safety of the equipment and personnel involved to continuouslyscan for variables which are in an abnormal unsafe range. The scanningoperation should, therefore, have a relatively high order of priority onthe use of the computer 8. However, numerous other operations areperformed by the monitoring system other than scanning for abnormalvariables, such as periodically feeding data on all the variables to anoutput device 10 which may be an electric typewriter. In other words,many demands are made on the computer 8 other than the demand forhandling the signals obtained from the transducers 2. Since it takes thescanner 4 a certain finite time to get set to receive new informationand to feed it to the analog to digital conviefter 6 or to switch fromone point to another, the computer 8 may perform other functions Whilethe scanner is getting set. Normally, a scanner is provided with meansfor generating a signal which indicates whether the scanner ormultiplexer is ready to receive information from the transducer 2 and totransmit information to the analog to digital converter 6, such signalbeing fed to the computer 8 to prevent the coupling of the outputthereof of the analog to digital converter, before it is connected orgated to the computer input. This signal is sometimes referred to as anot busy" or ready signal. In FIG. 1, this signal is assumed to bepresent on a line 14 extending from the scanner 4. For similar reasons,the output device such as the typewriter is frequently provided withmeans for signaling when the output device is busy or not busy, so thatthe computer 8 may utilize the output device when it is ready to beutilized and not at other times. In FIG. 1, this not busy signal isassumed to be fed from the typewriter 10 on a line 16.

In accordance with one aspect of the present invention, instead ofconnecting the not busy or ready lines 14 and 16 associated with thescanner 4 and output devices directly to the computer, these lines areconnected to interrupt demand terminals 18-2 and 18-6 of an interruptcontrol and register means generally indicated by reference numeral 18.These ready signals along with other demand signals to be described areutilized to initiate respective program routines stored in the computermemory which are assigned different priority levels. Later on in thespecification, an examplary detailed description will be given of asimplified scanning program routine initiated by the ready signal fromthe scanner 4 to illustrate the general manner in which the ready or notbusy signals are handled. The exemplary monitoring system is one whichis capable of handling demand signals for fifteen different levels ofpriority. The program routine initiated by the ready signal of thescanner 4 will be assigned the second highest priority level No. 2.

In the exemplary application of the invention to be described, thecomputer 8 is to respond to periodic timing signals generated by a timer20 which, for example, are to be counted and stored in the computermemory, and at the appropriate time will initiate a program routinewhich prepares the scanned data for readout to the typewriter 10. Thesetiming signals could, of course, be utilized for various other purposesalso. The timer 20 has an output line 20' connected to an interruptdemand input 18-1 of the interrupt control and register means 18 whichsignal will initiate operation of a program routine stored in thecomputer memory which handles this timing signal in a desired manner.This program routine must of necessity be given the highest prioritylevel No. 1.

A number of manual demand switches generally indicated by referencenumeral 22 in FIG. 1 are provided to initiate certain operations of thecomputer 8, such as preparing and feeding data stored in the computermemory to the typewriter 10, changing alarm set points, etc. In theexemplary form of the invention to be described these switchesrespectively initiate simplified program routines which prepare all thedata values stored in the computer memory for readout to the typewrtier10 and to select and prepare the highest data value stored in thecomputer memory for readout to an output display unit 10'. Lines 24 and24' extend from these manual switches to inputs 18a and 18b of theinterrupt control and register means 18. It will be assumed that theseswitches will initiate operation of a single shared program routinestored in computer memory assigned priority level No. 5. This programroutine will have separate subroutines each for carrying out one of theswitch operations referred to, if the associated switch is momentarilyoperated. The signals generated by the manual switches 22 are sometimesreferred to as C bit demand signals. In the example of the invention tobe described, up to fifteen different C bit demand signals can begrouped into various combinations. The drawings show three signals pergroup, each group sharing one of five possible priority levels. However,by adding additional circuits or chanels to the circuit to be described,all the C bit demand signals could share one or more routines. Only theoperation of two C bit signaling switches sharing one priority levelwill be described in detail since this is sufficient to illustrate thisaspect of the invention. The operation of any one C bit signaling meansin each group is effective to generate an interrupt demand signal on aline 25 extending from the interrupt control and register means 18 andre-entering the same at an interrupt demand input 18-5. The interruptcontrol and register means 18 includes a register to be described forregistering the presence of C bit demand signals as C bit markers" sothat, when a shared program routine is activated, the program routinecan select by a conditional transfer program step particular programsub-routine or sub-routines which correspond to the C bit demand signalor demand signals which activated the shared program routine. Theaforementioned register to be called the interrupt register also storesinformation as A bit markers on interrupt demand signal input terminals18-1-18-15 which receive momentary or persisting interrupt demandsignals. There are fifteen C bit marker positions C1 through C15 in theinterrupt register for the aforesaid fifteen possible C bit demandsignals and fifteeen A bit marker positions Al through A15 for theaforesaid fifteen possible interrupt demand signals. The numbers 1through 15 following the A refer to markers for priority levels 1through 15.

The interrupt demand inputs of the interrupt control and register means18 designated by reference numerals 18-1, 18-2, 18-5 and 18-6 arerespectively connected to circuits which will record A bit markers forpriority levels Nos. 1, 2, 5 and 6 respectively.

The priority interrupt demand signals may be simultaneously present onthe interrupt signal input terminals 18-], 18-2-18-n. The computer 8cannot respond to all of the demand signals at the same time since it iscapa ble of carrying out only one program step at a time. In order toutilize the various input signals to the device most efficiently, thecomputer 8 should respond to the interrupt demand signals in order ofthe importance or priority of the program routines which they activate.If the computer 8 is carrying out a given program routine assigned agiven priority level which is lower than the priority level of any otherdemanded routine, the current routine should be interrupted so that thehigher priority level routines called for can be carried out first. Tothis end, the interrupt control and register means 18 has stored thereininformation as R bit markers which indicate the priority level ofprogram routines in progress and also of program routine or routineswhich have been interrupted and not yet completed. The R bit marker forpriority level No. 1 is referred to as the R1 bit marker, the R bitmarker for priority level No. 2 is referred to as the R2 priority bitmarker and the R bit marker for the remaining levels are respectivelyreferred to as the R3, R4 R15 markers. These markers are reset, that isremoved, when their routines are completed. The interrupt register andcontrol means also stores C1 through C15 and B1 through B15 bit markerswhich respectively indicate the C bit demand signals which have not yeteffected a program interrupt operation and the presence of successive orpersistent interrupt demand signals in conjunction with the associated Rbit markers. Interrupt and lock-out operations are controlled by thesemarkers in a manner to be described later on in this specification.

In accordance with still another aspect of the present invention, theinterrupt register and control means 18 control the energization of Rbit indicator lamps 19-1 through 19-15 to indicate the presence ofprogram routines which have been activated but which are not yetcomplcted.

In addition to the various program routines which are operated directlyby the interrupt demand signals on the terminals 18-1, 18-2, etc., otherprogram routines are set up which are initiated by signals generatedwithin the computer 8, which signals are referred to as pseudo interruptdemand signals. The pseudo interrupt-responsive routines are assigneddistinctive priority levels. These priority interrupt signalseffectively establish links between various program routines and arehandled by the interrupt control and register means 18 in the same wayas are the other interrupt demand signals fed to the terminals 18-1,18-2, etc. The provision of pseudo interrupt signals establishessubstantial simplification and fiexibility in programing. For example,routines can be set up which are used in common by other routines and tosafeguard various intermediate results obtained by the common routine,the shared routine is given a higher priority level than any of theroutines which demand its operation. In the exemplary form of theinvention to be described, a common shared routine has been assignedpriority level No. 3 and the routines which demand its operation havebeen assigned priority levels Nos. 4 and 5. The program routine whichhas been assigned priority level No. is the one operated by the C bitmanual switches 22.

When the computer 8 is idling, that is, when no interrupt demand signalsare present, the computer will automatically carry out some basicroutine assigned the lowest priority level. No interrupt demand signalis necessary to enter this routine and no A, R, C or B bit markers areassociated with this routine.

Tables I and IA illustrate various program routines which will bereferred to in describing the operation of the present invention, thenature of the signals which initiate these routines, and the broadfunctions carried out thereby.

In accordance with still another aspect of the present invention, whenan interrupt demand signal persists after the program routine demandedby it has been completed, the routine is locked out and cannot bere-activated until the interrupt demand signal disappears and is reestablished again. The presence of a B bit marker and the absence of acorresponding A and R bit marker will cause a lockout operation of theroutine involved. (Lockout of C bit shared routine is not permitted forreasons because C bit demand signals are not effective to setcorresponding A bit markers until the C bit demand signals disappear. Ifthe C bit demand signals resulted in A bit markers during theiroccurrence, the persistence of one C bit signal could prevent operationof the shared routine by the other associated C bit demand signal. Theabsence of lockout of a C bit initiated routine is prevented also byother features of the invention to be explained later on in thespecification.

In accordance with still another aspect of the present invention, thedisappearance and reestablishment of an interrupt demand signal otherthan a C bit interrupt demand signal during the activation of a programroutine will set a corresponding B bit marker instead of an A bit markerwhich, upon completion of the routine, will set another A bit marker toeifect another interrupt operation.

Table II summarizes the various combinations of A, B and R bit markersto which the monitoring system of the invention responds and the meaningof these combinations.

PART IISPECIFIC DESCRIPTION (a) Patchboard 30 Although the interruptcontrol and register means indicated by box 18 in FIG. I may take avariety of forms, and could even be partially, at least, incorporated inthe computer itself, it is preferred that it have the featuresillustrated in the circuit diagram of FIGS. 3 and 3A. To

Table II to be explained.) Whenever a routine is completed, if an A B Rinterrupt demand is still present, the associated A bit 0 0 0 No demand,level not active. marker involved is removed and a B bit marker is set 10 0 Demand marked, level not active. which prevents the demand signalinvolved from effect- 1 0 1 Level activated, demand signal persists. inga subsequent interrupt operation. When the demand 5 0 0 1 Levelactivated, demand signal removed. signal involved disappears, theassociated B bit marker 0 l 1 Level activated, second demand marked. isautomatically removed to permit an interrupt opera- 0 l 0 Activitycompleted, demand signal persists. tion when the interrupt demand signalis later re-estab- 1 1 0 Cannot occur. lished. 1 1 1 Cannot occur.

Table 1 Priority level Interrupt demand signals Functions (1) Timeresponsive routine (2) Multiplexer input routine t,

busy.

(3) Binary to decimal conversion routine External demand signal (very 15seconds Demanded by signal that multiplexer is not [(1) Pseudo interruptfrom level 4 t. 3(2) Pseudo interrupt from level 5,

Counts time pulses. (i) Reads a multiplexer input. (3) Processes andstores data. (3) (omits nuinln-r olreadings. ronvtrts binary numbers todecimal form for output.

t l (1) Pseudo interrupt. from level 1 im 3 l1 1ur \lroecsscs storeddata for out iut ever hour or Log Prcpdmuon routine i9) lStll(l1O]i]Jbtll'Ll[ll. from level 5 if uxturliully I when dm mdm], l y

1 einnm or I G hits produced liyinanuul switches: Examines C hits. llC1, then transfers to log Operators rvriuvslswlmlw P11011111 s minim. ll02, a Dprl'onpg Search [or L2=l ind and convert largest value highestvalue.

(7) Printer output routinohw (8) Visual display output routine Not usedNonc Pseudo interrupt from level -i Pseudo interrupt from level 5 Outputroutine to output device it] (Typewriter). Output routine to outputdevice 10 (Visual display).

Computer idles when no interrupt. is demanded.

Table IA Priority level Programmed demands for ulhor levels (1) Timeresponsive routino (2) Multiplexer input routine..

(3) Binary to decimal conver- None.

sion routine.

(4) Log data preparation Causes pseudo interrupt to level 3 routine.pseudo interrupt to level 7 for output.

(1) Causes pseudo interrupt to level 4 ll (11 hit is present.

(2) Causes pseudo interrupt to level 3 for conversion. 'lhen pseudointerrupt to level 8 for output.

[5) Operators requests routiiio The problem of lockout is avoided inpart in the case of routines demanded by C bit interrupt demand signalsaid in understanding the circuitry there shown, a detailed box diagramof the interrupt control and register means 18 is shown in FIG. 2 whichindicates the functions of various sections of the circuit, the portionsrepresented by the boxes in FIG. 2 being indicated by dashed boxes inFIGS. 3, 3A, 3B, 3C and 3D. Also, the interconnection between theinterrupt control and register means 18 and the Elliott 803 Computer 8are shown by identically designated connecting points in FIGS. 3, 3A,3B, 3C and 3D, and FIGS. 5, 5A and 5B showing only a part of the ElliottComputer disclosed in said Handbook for the NationalElliott 803Computer."

The input circuit of the interrupt register and control means 18includes a patchboard 30 (FIG. 3). The patchboard 30 has a left handcolumn of terminals to which the interrupt demand signaling means areconnected, and a right hand column of terminals which may be permanentlywired to various portions of the circuitry to be described. Forconvenience to the operator in

1. IN A MONITORING SYSTEM INCLUDING PROGRAM MEANS FOR PROVIDINGDIFFERENT PROGRAM ROUTINES EACH OF WHICH, BY VARIOUS BASIC STEPS EFFECTIN SEQUENCE, CARRIERS OUT A DIFFERENT FUNCTION, THE IMPROVEMENT IN APOLARITY INTERRUPT SYSTEM FOR AUTOMATICALLY OPERATING SAID ROUTINES INACCORDANCE WITH PREDETERMINED PRIORITY LEVELS ASSIGNED TO THE RESPECTIVEROUTINES, SAID PRIORITY INTERRUPT SYSTEM COMPRISING: RESPECTIVESIGNALING MEANS FOR GENERATING INTERRUP DEMAND SIGNALS WHICH CALL FOROPERATION OF SAID PROGRAM ROUTINES; INTERRUPT REGISTER MEANS HAVING FOREACH PRIORTY LEVEL AND A BIT STORAGE MEANS FOR STORING A MARKERINDICATING THE PRESENCE OR ABSENCE OF AN INTERRUPT DEMAND SIGNAL FOR THELEVEL INVOLVED AND AN R BIT STORAGE MEANS FOR STORING A MARKERINDICATING THE CURRENT ACTIVITY OR INACTIVITY OF A PROGRAM ROUTINEHAVING THE PRIORITY LEVEL INVOLVED; MEANS FOR SETTING AN R BIT MARKER INTHE R BIT STORAGE MEANS OF A GIVEN PRIORITY LEVEL WHEN THE PROGRAMROUTINE OF THE PRIORITY LEVEL HAS BEEEN ACTIVATED AND FOR REMOVING THE RBIT MARKER WHEN THE ROUTINE IS COMPLETED, MEANS RESPONSIVE TO THEPRESENCE OF AN INTERRUPT DEMAND SIGNAL FOR A PRIORITY LEVEL AND THEABSENCE OF CORRESPONDING A AND R BIT MARKERS IN SAID INTERRUPT REGISTERMEANS FOR SETTING AN A BIT MARKER IN THE A BIT STORAGE MEANS FOR THEPRIORITY LEVEL INVOLVED; MEANS RESPONSIVE TO THE BASENCE OF AN INTERRUPTDEMAND SIGNAL AND THE PRESENCE OF AN R BIT MARKER FOR A GIVEN PRIORTIYLEVEL FOR REMOVING THE CORRESPONDING A BIT MARKER ONCE THE ROUTINEINVOLVED IS ACTIVATED; PRIORITY STATUS SCANNING MEANS FOR SEQUENTIALLYEXAMINING THE INFORMATION IN SAID A AND R BIT STORAGE MEANS OF SAIDINTERRUPT REGISTER MEANS IN THE ORDER OF HIGHEST PRIORITY FIRST, SAIDPRIORITY STATUS SCANNING MEANS INCLUDING MEANS RESPONSIVE TO THEPRESENCE OF AN A BIT MARKER AND THE ABSENCE OF AN R BIT MARKER FORINTERRUPTING THE PROGRAM ROUTINE IN PROGRESS, MEANS FOR STORINGINFORMATION ON THE POINT OF THE INTERRUPTED ROUTINE AT WHICH THEINTERRUPTION TOOK PLACE AND INITIATING OPERATION OF THE HIGHER PRIORITYLEVEL ROUTINE, AND MEANS OPERATIVE AFTER COMPLETION OF THE HIGHERPRIORITY LEVEL ROUTINE FOR RESUMING THE INTERRUPTED PROGRAM AT THE POINTOF INTERRUPTION THEREOF.